In the past the density of semiconductor devices in integrated circuits has been limited by the space required for adequate isolation between devices. For example, in conventional NPN bipolar transistor integrated circuits, isolation between adjacent N-type beds is usually achieved by providing P+ diffused regions in the N-type epitaxial layer extending from the surface down to the P-type substrate. The epitaxial N-type layer is usually on the order of three to four microns in thickness which means that the diffusion must be carried out through this depth. The width of these diffused regions is in the order of 6 to 8 microns. In forming devices in the N-type regions, P+ diffusions are carried out. However, these are much shallower than the P+ diffused regions extending down to the substrate and, therefore, must be carried out separately. Since these diffusions are separate operations, allowance must be made for alignment variations. In addition, if the P+ diffused regions are too close to the P-type base diffusions, space charge problems may be encountered. By way of example, in practice it has been found that in forming NPN bipolar transistors, a spacing of approximately 23 microns is required between the bases of adjacent transistors. In addition, it has been found that even where dielectric isolation is provided between N-type beds, there is some leakage between the beds. In MOS devices where dielectric isolation has been provided between islands, channel leakage occurs in N channel devices which is caused by normal inversion at the oxide interface and leakage under applied voltage occurs with respect to the metal leads utilized for interconnecting MOS devices. Also, in MOS devices there is a need for closer spacing. There is, therefore, a need for a new and improved semiconductor structure and method which will overcome the above named limitations.